Field
The present disclosure relates generally to high-speed data communications interfaces, and more particularly, to transmitted preamble sequences used for receiver calibration and mode signaling in multiphase data communication links.
Background
Manufacturers of mobile devices, such as cellular phones, may obtain components of the mobile devices from various sources, including different manufacturers. For example, an application processor in a cellular phone may be obtained from a first manufacturer, while the display for the cellular phone may be obtained from a second manufacturer. Application processors, displays and/or other devices may be interconnected using a physical interface that may be standards-based or proprietary in design. In one example, the physical interface may conform to standards specified by the Mobile Industry Processor Interface (MIPI) Alliance, such as the MIPI C-PHY standard, which is a multi-wire, physical layer interface for camera and display applications, for example.
In a multi-wire interface, the maximum speed of the communication link and the ability of a clock-data recovery (CDR) circuit may be limited by the maximum time variation related to transitions of signals transmitted on the communication link. Transitions on different wires may exhibit different variations in signal transition times, which can cause the outputs of receivers in a receiving device to change at different times with respect to a data or symbol boundary. Large transition time differences in multi-wire signals often requires the implementation of a delay element or circuit in the CDR circuit, where the delay element has a minimum delay that is at least as long as the difference between the minimum and maximum receiver transition events. The maximum time of this delay element can restrict the throughput on the communication link by significantly limiting the period of the transmission clock. Moreover, the maximum time of the delay element may vary with operating conditions, including process, voltage, and temperature.
Accordingly, it is useful to calibrate the delay elements or circuits in a receiver to optimize the performance of the CDR circuit, particularly at higher symbol rates. An effect of this calibration is that it greatly minimizes process, voltage, and temperature variations of the delay elements in the CDR circuit. The delays in the CDR circuit are used to mask multiple signal transitions at a symbol boundary so that the symbol clock can be recovered in a reliable manner. The delay must be long enough to sufficiently mask multiple transitions that result from lossy transmitter (Tx) to receiver (Rx) channels, but short enough so as to not encroach into the transition of the next symbol. If a Preamble including a sequence of symbols is used for calibration, but the calibration circuit needs a longer Preamble, it becomes difficult to coordinate between the transmitter and receiver when the Preamble will be transmitted with a sufficient duration to perform receiver calibration versus transmitting a minimal standard length Preamble to be used to transmit a data burst.